Today, the design of electronic devices no longer begins with diagramming an electronic circuit. Instead, the design of modern electronic devices, and particularly integrated circuits (“IC's”), often begins at a very high level of abstraction. For example, a design may typically start with a designer creating a specification that describes particular desired functionality. This specification, which may be implemented in C, C++, SystemC, or some other programming language, describes the desired behavior of the device at a high level. Device designs at this level of abstraction are often referred to as “algorithmic designs,” “algorithmic descriptions,” or “electronic system level (“ESL”) designs”. Designers then take this algorithmic design, which may be executable, and create a logical design through a synthesis process. The logical design will often be embodied in a netlist. Frequently, the netlist is a register transfer level (“RTL”) netlist.
Designs at the register level are often implemented by a hardware description language (“HDL”) such as SystemC, Verilog, SystemVerilog, or Very High speed hardware description language (“VHDL”). A design implemented in HDL describes the operations of the design by defining the flow of signals or the transfer of data between various hardware components within the design. For example, an RTL design describes the interconnection and exchange of signals between hardware registers and the logical operations that are performed on those signals.
Designers subsequently perform a second transformation. This time, the register transfer level design is transformed into a gate level design. Gate level designs, like RTL designs, are also often embodied in a netlist, such as, a mapped netlist for example. Gate level designs describe the gates, such as AND gates, OR gates, and XOR gates that comprise the design, as well as their interconnections. In some cases, a gate level netlist is synthesized directly from an algorithmic description of the design, in effect bypassing the RTL netlist stage described above.
Once a gate level netlist is generated, the design is again taken and further transformations are performed on it. First the gate level design is synthesized into a transistor level design, which describes the actual physical components such as transistors, capacitors, and resistors as well as the interconnections between these physical components. Second, place and route tools then arrange the components described by the transistor level netlist and route connections between the arranged components. Lastly, layout tools are used to generate a mask that can be used to fabricate the electronic device, through for example an optical lithographic process.
In general, the process of generating a lower-level circuit description or representation of an electronic device (such as an RTL netlist or a gate level netlist), from a higher-level description of the electronic device (such as an algorithmic description,) is referred to as “synthesis.” Similarly, a software application used to generate a lower-level design from a higher-level design is often referred to as a “synthesis tool.”
Concurrent Designs
Modern hardware designs are becoming increasingly complex and often include multiple component blocks specially designed to perform particular tasks or functions. Additionally, these designs are often capable of concurrently processing multiple tasks simultaneously. As used herein, a “concurrent design,” is a design that allows for the simultaneous execution of more than one process. In many cases, these simultaneously executing processes interact with each other. Design of “concurrent systems” is facilitated by the use of high-level algorithmic descriptions, as described above, wherein many of the functions defined by the algorithmic description are non-sequential. More particularly, many of the operations and functions (i.e. the non-sequential ones) do not have to be executed in a particular order.
Synthesizing a non-sequential algorithmic description for a circuit, results in a logical design that allows for the parallel execution of hardware processes. These concurrently executing processes share access to the same memory storage locations and often to the same data stored in memory. More particularly, a number of memory storage locations, such as, for example, a memory register, which will correspond to a variable in the algorithmic description, can be accessed by multiple processes. These shared memory locations are often referred to as “shared variables.” The timing of access to these “shared variables” by the different concurrent processes can cause the results of the process to differ. Although both results are valid, as those of skill in the art can appreciate, verification of a non-sequential algorithmic description against a synthesized logical design is difficult due to the results differing depending upon event execution and timing.